Selected Publications

	J. Liu, K. Sundaresan, and N.R. Mahapatra, "A Fast Dynamic Compression Scheme for Low-Latency On-Chip Address Buses," Proc. 4th Workshop on Memory Performance Issues (WMPI 2006), held in conjunction with 12th High Performance Computer Architecture (HPCA 2006), Austin, TX, Feb. 11, 2006.
	J. Liu, K. Sundaresan, and N.R. Mahapatra, "A Fast Dynamic Compression Scheme for Low-Latency On-Chip Address Buses," ACM SIGMICRO Newsletter, Vol. 24, no. 1, Apr. 2006. (Selected top paper from the 4th Workshop on Memory Performance Issues (WMPI 2006))
	J. Liu, K. Sundaresan, and N.R. Mahapatra, "Efficient Encoding for Address Buses with Temporal Redundancy for Simultaneous Area and Energy Reduction," Proc. 16th Great Lakes Symposium on VLSI (GLSVLSI 2006), pp.111-114, Philadelphia, PA, Apr. 30-May 2, 2006.
	J. Liu, B. Bell, and T. Truong, "Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance," Proc. 1st International Multi-Symposiums on Computer and Computational Science, vol. 1, pp.389-396, Hangzhou, China, Jun. 20-24, 2006.
	J. Liu, K. Sundaresan, and N.R. Mahapatra, "Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses," Proc. 24th IEEE International Conference on Computer Design (ICCD 2006), pp.17-24, San Jose, CA, Oct. 1-4, 2006.
	N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "A limit study on the potential of compression for improving memory system performance, power consumption, and cost," Journal of Instruction-Level Parallelism, vol. 10, Jul. 2005. Available: http://www.jilp.org/vol7/index.html
	J. Liu, K. Sundaresan, and N.R. Mahapatra, "Energy-efficient compressed address transmission," Proc. 18th IEEE International Conference on VLSI Design (VLSID 2005), pp.592-597, Kolkata, India, Jan. 3-7, 2005.
	J. Liu, K. Sundaresan, and N.R. Mahapatra, "Dynamic address compression schemes: A performance, energy, and cost study," Proc. 22nd IEEE International Conference on Computer Design (ICCD 2004), pp.458-463, San Jose, CA, Oct. 11-13, 2004.
	N.R. Mahapatra, J. Liu, and K. Sundaresan, "Hardware-only compression of underutilzed address buses: design and performance, power and cost analysis," Proc. 21st IEEE International Conference on Computer Design (ICCD 2003), pp.234-239, San Jose, CA, Oct. 13-15, 2003.
	N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "The potential of compression to improve memory system performance, power consumption, and cost," Proc. 22nd IEEE International Performance, Computing, and Communications Conference (IPCCC 2003), pp. 343-350, Phoenix, AZ, Apr. 9-11, 2003.
	J. Liu, N.R. Mahapatra, and K. Sundaresan, "Hardware-only compression to reduce cost and improve utilization of address uses," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), pp. 220-221, Tampa, FL, Feb. 20-21, 2003.
	J. Liu, N.R. Mahapatra, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "Memory system compression and its benefits," Proc. 15th Annual IEEE International ASIC/SOC Conference (ASIC/SOC 2002), pp. 41-45, Rochester, NY, Sep. 25-28, 2002.
	N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "The performance advantage of applying compression to the memory system," Proc. ACM SIGPLAN Workshop on Memory System Performance (MSP 2002), held in conjunction with ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation (PLDI 2002), Berlin, GERMANY, Jun. 16, 2002.
	N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "An analysis of the potential of compression in improving memory system performance, power consumption, and cost," Proc. 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with 29th International Symposium on Computer Architecture (ISCA 2002), Anchorage, AK, May 25, 2002.
	J. Liu, "Information technology and multimedia communications," Proc. Computer Technology and Human Future, pp. 88-91, Beijing, P. R. China, June, 1999.