All computer systems have three main subsystems: the computation system, the memory system, and the I/O system. The memory system has two main types of components: storage components (including registers, one or more levels of caches, main memory) for storing information (primarily instructions and data) and communication components (comprising I/O buffers, I/O pads, and pins on the processor and memory chips, and on- and off-chip control, address, instruction, and data buses) for communicating information (primarily addresses, instructions, and data) between the computation system and storage components and between the storage components themselves.

A combination of dramatic technological and architectural advancements has resulted in an exponential trend for
computation system performance enhancement. This, coupled with slower speed improvements of on- and off-chip interconnect, caches, and DRAM, has contributed to a growing computation-memory system performance gap [1]. To address this problem, the fraction of the processor chip devoted to storage (registers, caches) and communication (I/O buffers and pads, on-chip buses) components has increased and so also has the number and size of off-chip storage (off-chip caches, main memory) and communication (pins, off-chip buses) components [1]. Moreover, in nanometer regime, interconnect size scales relatively poorly compared to logic size, and not only do individual wire capacitances contribute to power consumption, but more so do interwire capacitances between adjacent on-chip bus lines due to tighter spacing between higher aspect-ratio wires [2]. Consequently, increasingly more fraction of the system power consumption and cost is due to the memory system compared to the computation system [3]. Thus, the memory system is becoming an increasing bottleneck as designers strive towards higher performance, cost-effective, and power-efficient system designs.

In our research, we consider the following three types of redundancies related to information communicated and
stored in the memory system, with the main focus being on information communicated on nanometer-scale memory system buses. Temporal redundancy refers to the fact that there are time periods when memory system components carry no or non-performance-critical information (e.g., idle buses and invalid, stale, and "dead" blocks in caches). Spatial redundancy means redundancy in the number of bits used to represent information, which causes more resources (e.g., bus lines or memory cells) to be engaged than necessary-information compression techniques address this. Finally, energy redundancy implies expending more than the required energy to communicate or store information; encoding schemes attempt to minimize this redundancy via energy-efficient information representations.

To take advantage of these redundancies, we are analyzing and designing information pattern aware memory
(IPAM) systems that exploit patterns in information communicated and stored in a multi-level memory hierarchy
to derive gains in performance, power consumption, and cost. Our schemes seek to exploit temporal locality, spatial locality, first order temporal context, statistical, association, correlation, and cluster patterns, among others, using statistical and data mining techniques. We consider address, instruction, and data information, all types of communication (on- and off-chip buses and associated circuitry) and storage (registers, caches, main memory, TLB, and page table) components at different memory levels, and various target system (embedded, desktop, server) and application (e.g., DSP, multimedia, integer-intensive, scientific) scenarios.